The present invention relates to a memory apparatus which is divided into a plurality of memory banks and is managed by two-dimensional addresses.
In printers which print a two-dimensional pattern, such as a character pattern or the like, print data is not necessarily given in the order in which the data is outputted, but the data transmitted is outputted to specified locations in a page. Therefore, a control apparatus of such printers is provided with a memory having a capacity corresponding to a print paper and a dot pattern is printed at the specified locations corresponding to an output page. The memory corresponding to the print paper is managed by two-dimensional addresses (X, Y addresses) to make the memory locations correspond to the physical coordinates on the paper.
In such a print control apparatus, memories corresponding to a print paper consisting of as much as two pages are ordinarily provided since a method whereby the next page is stored while a certain page is outputted is generally adopted. In such a case, if the next one page is not completely stored while one page is being outputted, the printer will have been stopped, so that it is necessary to effect a high-speed memory access. Therefore, there is generally adopted a method whereby the memory is divided into two or more banks and data is sequentially read from or written into a plurality of memory banks, thereby enabling a plurality of banks to be seemingly simultaneously accessed. In such print control method, for example, a memory managed by two-dimensional addresses for storing print data is divided into two memory banks and the memory banks are switched by the least significant bit of the X address. In this case, the correspondence among the X address, Y address and memory banks is as shown in FIG. 1. When a bit 2.sup.0 of the X address is zero (namely, the X address is even) a bank 0 is selected, when the bit 2.sup.1 of X is 1 (X is odd) another bank 1 is selected.
In case of developing a character pattern in such a memory on a character unit basis, dot patterns are developed sequentially from the upper line to the lower line of a character as shown in FIG. 2. Similarly, in case of developing vertical lines as shown in FIG. 3 as well, dot patterns are developed sequentially from the upper line to the lower line. Namely, in case of developing a character or vertical lines, the memory is accessed in the state whereby the X address is fixed while sequentially updating the Y address, so that memory requests are concentrated into one memory bank (memory bank 0 in FIGS. 2 and 3).
FIG. 4 shows a time chart showing situations of access to each memory bank in the cases where the X address is updated and where the Y address is updated in the above-described conventional print control apparatus. As shown in FIG. 4(a), in the case where the Y address is fixed and only the X address is updated, the banks 0 and 1 are alternately accessed. However, as shown in FIG. 4(b), in the case where the X address is fixed and only the Y address is updated, only one memory bank is continuously accessed, so that in spite of the fact that the memory is divided into two memory banks, the whole memory access time is substantially equal to that in the case where a memory is not divided into banks.
To cope with such a problem, a method whereby the apparatus is modified such that the memory banks are switched by the Y address is also considered. However, in case of developing horizontal lines or the like, the Y address is fixed and only the X address is continuously updated; thus, access requests are likewise concentrated into one memory bank as well.